Due to the ever-increasing complexity of new IC devices, Electronic Design Automation (EDA) software tools are now considered essential in the process of converting each new electronic system idea into a corresponding physical integrated circuit (IC) device (“chip”). That is, IC designers utilize EDA tools to develop an initial IC design (i.e., software description) that they believe is capable of implementing a new electronic system idea, to analyze and modify the initial IC design in order to verify that the final IC design performs the operational objectives set for the electronic system idea, and then to generate and check a series of IC layouts (aka mask designs or mask layouts) that define a physical IC chip capable of implementing the final IC design. Because modern IC devices, such as System-on-Chip (SoC) devices, can comprise billions of individual circuit components, there is no practical way to develop and produce modern IC devices without the use of EDA tools.
To further speed up IC development, IC designers typically utilize blocks to implement standard circuit functions. As used herein, the term “block” (aka Intellectual Property (IP) core) refers to a unit of IC layout that is configured to perform a particular circuit function (e.g., a memory array having a certain capacity and speed, an adder, or a particular type of microprocessor) that is commonly utilized in modern SoC designs. EDA tools typically facilitate the re-use of blocks during IC development by way of providing libraries from which selected blocks may be retrieved and placed into a new IC design. In addition, each block includes various types of circuit and layout description information that are utilized during subsequent simulation, static verification, synthesis, and place-and-route operations performed by the EDA tool. In effect, the re-use of previously developed blocks saves IC development time by way of providing a “known-good” (i.e., pre-tested) circuit/layout design that is capable of implementing a required circuitry function, whereby the IC designer avoids the time-consuming process of developing a new circuit from scratch, thereby increasing profitability by reducing the amount of time and resources required to complete and fabricate each new IC design.
Although the reuse of a selected block in a new IC design provides the benefits set forth above, a problem can arise during the design of multi-level power managed systems when power-state combinations required by a new IC design conflict with power-state combinations associated with the selected block. That is, in addition to IC layout information, each block typically includes a Unified Power Format (UPF) design language file that describes certain combinations of power supply voltage levels (or “off”) for which the block's circuit was designed to operate properly. During IC development, an IC designer typically generates top-level IC design descriptions into which blocks are incorporated, and specifies associated top-level power-state combinations that are stored in a top-level UPF design file. One type of power-state combination conflict includes voltage level conflicts that occur when blocks developed for high-power IC devices (e.g., devices developed for 1.5V supplies) are reused in lower-power IC designs (e.g., devices developed for 1.2V supplies), whereby the upper voltage levels listed in the block-level UPF design file are typically different than those provided in the top-level UPF design file. The conflicting power-state combination problem can also arise when an IC designer specifies certain power-state combinations in top-level UPF design file that conflict with the block-level power-state combinations. EDA tools typically address the conflicting power-state combination problem by retaining only overlapping power-state combinations (i.e., power-state combinations that are present in the UPF design files of both the blocks and the top-level IC design description), and by removing (deleting) all inconsistent power-state combinations from the block and top-level UPF design files. This automated process often leads to the undesirable elimination of required power-state combinations included in the top-level IC design description because they are inconsistent with the block-level power-state combinations, which can lead to improper operation of the IC device fabricated using the modified IC design description. Moreover, it is not always immediately obvious that required power-state combinations have been eliminated by an EDA tool. Once an IC designer realizes that required power-state combinations have been eliminated, the only current solution is for the IC designer to manually change the reused block (IP core) design files, which is incompatible with the concept of reusing the blocks. Moreover, manual modification of the blocks is risky because the changes may not satisfy the IC design, and the modified block may require unexpected additional changes to adapt to the new voltages.
What is needed is an automated method for addressing the above-mentioned conflicting power-state combination problem as early as possible during the development of multi-level power managed IC systems. That is, what is needed is an EDA tool that is configured to identify and address conflicting power-state combinations in multi-level power managed IC designs (i.e., software-based descriptions) in a way that avoids the undesirable elimination of critical power-state information. What is particularly needed is an EDA tool that automatically resolves conflicting power-state combinations that are compatible (fixable), and notifies the IC designer about each incompatible conflict so that every conflict can be resolved before further development is performed.